Design Methodology Engineering Intern

Job Title: Design Methodology Engineering Intern

Location: Canada

Job Description: to learn. While a solid foundation in digital design (VHDL, Verilog) and scripting ability is desired, it is not strictly…) Preferred Qualifications: Linux Experience: bash, tcsh Programming Languages: C, C++, Python, VHDL, SystemVerilog, TCL

Company Name: Intel

Salary:

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